1. Field of the Invention
The invention relates generally to a flash memory device and a method of driving the same, and more particularly, but without limitation, to a flash memory device that can minimize a variation in a threshold voltage distribution caused by coupling between cells, and a method of driving the same.
2. Description of the Related Art
Flash memories, which are widely used nonvolatile memory devices, can electrically erase or rewrite data. As compared to magnetic disk storage media such as a hard disc, a flash memory has lower power consumption and a shorter access time.
A flash memory is classified as a NOR flash memory or a NAND flash memory according to the connection between memory cells and bit lines. The NOR flash memory, in which at least two cell transistors are coupled in parallel to a single bit line, stores data according to a channel hot electron method and erases data according to a Fowler-Nordheim tunneling method. On the other hand, the NAND flash memory, in which at least two cell transistors are coupled in series to a single bit line, stores and erases data according to the F-N tunneling method. Conventionally, the NOR flash memory has a large current consumption, and thus, is disadvantageous in terms of high integration. An advantage of the NOR flash memory is the ability to cope with high-speed operation requirements. Since the NAND flash memory uses a lower cell current than the NOR flash memory, the NAND flash memory is advantageous in terms of high integration.
FIG. 1A is a circuit diagram of a memory cell structure of a conventional NAND flash memory. Referring to FIG. 1A, a plurality of word lines WL11 through WL14, and a plurality of memory cells M11 through M14 are shown. The memory cells M11 through M14 form a string structure along with selection transistors ST1 and ST2, and the memory cells M11 through M14 are coupled in series between a bit line BL and a ground voltage VSS. Since the conventional NAND flash memory uses a lower cell current than the NOR flash memory, a programming operation is performed only once on all the memory cells coupled to a single word line.
FIG. 1B is a circuit diagram of a memory cell structure of a conventional NOR flash memory. Referring to FIG. 1B, in the conventional NOR flash memory, each of the memory cells M21 through M26 are coupled between a bit line BL1 or BL2 and a common source line CSL1 or CSL2, respectively. Since the conventional NOR flash memory consumes a large amount of current during its programming operation, a predetermined number of memory cells can be programmed by a single programming operation.
Multi-level cell (MLC) technology is one method for increasing the storage capacity of flash memory. The MLC technology involves storing at least two data bits in a single cell by programming the cell using different threshold voltages. This technology is differentiated from single level cell (SLC) technology involving storing one bit in a single memory cell.
According to an MLC programming method of storing 2-bit data in each cell, each memory cell has one of these states: ‘11’, ‘10’, ‘01’, and ‘00’. A memory cell with the state of ‘11’ is an erased cell and has the lowest threshold voltage. A memory cell with one of the states ‘10’, ‘01’, and ‘00’ is a programmed cell and has a higher threshold voltage than the cell with the state of ‘11’. On the other hand, according to an MLC programming method of storing 3-bit data in each cell, each memory cell has one of these states: ‘111’, ‘110’, ‘101’, ‘100’, ‘011’, ‘010’, ‘001’, and ‘000’. A memory cell with the state of ‘111’ is an erased cell and has the lowest threshold voltage. Memory cells in the other states are programmed cells, and have higher threshold voltages than the cell with the state of ‘111’.
FIG. 2 is a graphical illustration of threshold voltage distributions for each operation of a programming operation in a 2-bit multi-level cell. In FIGS. 2(a) through 2(d), the vertical axis represents a number of cells, and the horizontal axis represents the threshold voltage. FIG. 2(a) illustrates an operation of programming least significant bit (LSB) data. When the operation of programming LSB data is performed, some cells have a LSB data value of “1”, and other cells have an LSB data value of “0”. If an LSB programming operation is performed by applying an incremental step pulse program (ISPP) to word lines, it is possible to increase a voltage interval of a step voltage in order to program LSB data at a higher speed. In this case, the programmed cells have a wide threshold voltage distribution.
Then, as shown in FIG. 2(b), the threshold voltage distribution of the LSB programmed cells becomes wider due to coupling between adjacent cells occurring in the programming process.
FIG. 2(c) illustrates an operation of programming most significant bit (MSB) data. From among cells with a LSB data value of “1”, a cell into which a MSB data value of “0” is loaded shifts to the state of “01”, and a cell into which the MSB data value of “1” is loaded remains in the state of “11”. Similarly, from among cells with the LSB data value of “0”, a cell into which MSB data value of “0” is loaded shifts to the state of “00”, and a cell into which MSB data value of “1” is loaded shifts to the state of “10”.
FIG. 2(d) shows that the threshold voltage distribution of the MSB programmed cells widens due to a coupling effect between adjacent cells. In other words, when a cell adjacent to a specific MSB-programmed cell is MSB-programmed to vary its threshold voltage, the level of the threshold voltage of the specific MSB-programmed cell may vary due to a coupling effect between the cells. In particular, FIG. 2(d) shows an example in which along with an increase in threshold voltage of an adjacent cell, the threshold voltage distribution of each of MSB-programmed states widens because of threshold voltage increases caused by the coupling effect between cells.
FIG. 3 is a graphical illustration of threshold voltage distributions for each operation of a programming operation in a 3-bit multi-level cell. In FIGS. 3(a) through 3(f), the vertical axis represents a number of cells, and the horizontal axis represents the threshold voltage. The threshold voltage distributions in FIGS. 3(a) through (d) are substantially similar to those of FIGS. 2(a) through (d). Through the operations illustrated in FIGS. 3(a) to (d), the LSB data (hereinafter referred to as ‘first data’) and the MSB data (hereinafter referred to as ‘second data’) are programmed into memory cells.
After a second programming operation illustrated in FIG. 3(c), a third programming operation illustrated in FIG. 3(e) is performed so that 3-bit data are stored in the memory cells. As programming is performed on an adjacent cell, the threshold voltage distribution widens due to coupling between the cells, as illustrated in FIG. 3(f).
A variation in threshold voltage due to coupling between cells is proportional to a variation in threshold voltage of an adjacent cell during programming.
Referring to FIGS. 3(d) and (e), in the case of programming from “11” to “011”, the variation in threshold voltage is the largest. Accordingly, the variation in threshold voltage caused by coupling between cells is relatively large when an adjacent cell is programmed from “11” to “011”.
The consequence of widening threshold voltage distributions, especially in multi-level cells, is a decrease in the reliability of data reads. Accordingly, as the number of bits stored in a single memory cell increases, the reliability of the nonvolatile memory device decreases. Improved flash memory devices, and methods of driving same, are therefore needed.